The invention relates generally to controlling a first-in-first-out (FIFO) buffer and more precisely to a FIFO controller for buffering a plurality of disparate data blocks or entities flowing between asynchronous data processes in a manner preventing overlap or corruption of data.
FIFO structures are well known for buffering data passing between two data handling processes which operate asynchronously with respect to each other. A FIFO memory is a structure wherein data words, objects, blocks, or entities are taken out of the structure in the order of receipt. A sender places data objects into the FIFO structure, while a receiver collects the objects from the structure.
Referring to FIG. 1, generally, a first-in-first-out (FIFO) buffer 44 is used to provide temporary storage for data that is being transferred between two or more asynchronous data processing systems. These data processing systems typically have specialized clocking circuits, e.g. Clk-1 and Clk-2 operating at predetermined frequencies (phases) which are asynchronous with respect to each other. The FIFO buffer 44 shown in the FIG. 1 example is, for example, a dual port memory array having a preferred row dimension of thirty two bits wide with thirty two rows in height or depth (i.e. a 32 by 32 memory array).
One typical data processing system is a disk-type magnetic recording system or disk drive 30. The disk drive 30 uses a magnetic transducer element, or head 31 to record information onto (i.e., write) and to retrieve information from (i.e., read) a magnetic medium formed on a surface of a rotating disk 32. Each storage disk 32 comprises an annular substrate onto which is deposited a magnetic recording medium. Although FIG. 1 shows a single head 31 and disk 32, in practice multiple storage surfaces and heads are frequently employed. In the FIG. 1 example the storage surface of disk 32 is divided into thousands of concentric, annular bands, or xe2x80x9ctracksxe2x80x9d 33 each having a predetermined radial extent. Each head 31 is supported in close proximity to an associated disk 32 surface by a head positioning assembly, or actuator 34, that supports the head 31 near the disk 32 surface and moves it from one radial position to another, thereby permitting use of a single head 31 for reading and writing along each of the multiple concentric tracks 33. The positioner assembly 34 for each head 31 or group of heads 31 includes an actuator arm 35 and an actuator motor 36. The actuator motor 36 moves the actuator arm 35 to change the position of the head 31 with relation to the tracks 33 on the disk 32. A disk drive 30 having a plurality of disks 32 stacked on a common spindle will typically employ a single actuator motor 36 to move a corresponding number of ganged-together actuator arms 35 and heads 31 in unison. A disk controller (not shown) controls operations of the disk spindle and the actuator motor 36.
The disk drive 30, further includes a disk channel 37, such as a partial-response maximum-likelihood (PRML) synchronous sampling data detection channel, for encoding, detecting, decoding and controlling flow of data read from or written to the disk 32 at a data rate in accordance with a disk clock CLK-1. The disk clock CLK-1 may remain fixed, or it may be varied as a function of radius of a particular data track 33 (since relative rotational velocity varies with track radius). The disk drive 30 typically transmits data back and forth between itself and a random-access-memory (RAM) buffer 25. The RAM buffer 25 includes one or a plurality of electronic data storage integrated circuit memory chips for storing data therein. The RAM buffer 25 is coupled with a RAM Port 26. The RAM Port 26 is coupled to the disk drive 30 via a disk-direct-memory-access (DDMA) 40, which is defined within the disk drive 30. The RAM Port 26 circuit is further connected to several other clients including: a RAM buffer manager 24; a standard bus interface 28, such as a Small-Computer-System Interface (SCSI), which connects to a host computer 22 and also may be connected as well as to several other clients (n). The RAM Port 26 circuit provides access arbitration among the clients seeking access to the RAM buffer 25, including the DDMA 40, host interface 28 and other clients (n) such as a disk drive controller.
The DDMA 40 generally includes a RAM Port Interface circuit 42, a FIFO buffer 44, and a disk interface circuit 45. The RAM Port interface 42 communicates data as well as control information to the RAM buffer 25 via the RAM Port 26 and RAM buffer manager 24. The FIFO buffer 44 is connected to the RAM Port Interface 42 circuit and acts as a temporary storage space for data that is in the process of being transferred to/from the disk drive 30 and the RAM 25. The disk interface circuit 45 is connected to the disk channel 37, via a bus 27, as well as to the FIFO buffer 44. The disk interface 45 operates to communicate data to/from the disk channel 37 and storage surface of disk 32.
The DDMA 40 further includes a disk read/write process control 41 and a RAM read/write process control 43. The disk read/write process control circuit 41 is connected to the disk interface 45 and is synchronous with CLK-1 of the disk channel 37. The RAM read/write process control circuit 43 is connected to the RAM Port interface 42 and is synchronous with a second clock CLK-2 used to write data to and from the RAM buffer 25. The disk and RAM read/write process control circuits 41, 43 enable the RAM Port interface 42 and the Disk Drive interface 45 to either read data from or write data to the FIFO buffer 44 depending on the direction of data flow between the RAM buffer 25 and the disk drive 30.
In a typical data transfer from the disk drive 30 to the RAM buffer 25, a plurality of data blocks written in tracks 33 are sensed as magnetic flux transitions by the head 31 and recovered as binary data by the disk channel 37. The recovered data is transmitted to the FIFO buffer 44 via the disk interface 45. Prior to writing data to the FIFO buffer 44, a write-pointer register 48 is preset to point to the first row of the FIFO 44. Next, the disk read/write process control circuit 41 is enabled for writing data to the FIFO buffer 44, and the RAM read/write process control circuit 43 is enabled for reading data from the FIFO buffer 44. Thereafter, the disk interface 45 begins writing 32-bit data segments to the FIFO buffer 44 synchronously with clock CLK-1. Additionally, the write-pointer address register 48 is incremented as each data segment is written into the FIFO buffer 44. Once the FIFO buffer 44 accumulates a predetermined number of data segments, a control signal is issued to the RAM Port Interface 42 indicating that the FIFO buffer 44 has data which needs to be read out.
At this point, the RAM Port Interface 42 arbitrates with the RAM Port 26 for direct access to the RAM buffer 25 via the RAM buffer manager 24. When access is granted to the RAM buffer 25, the RAM Port Interface 26 reads data out of the FIFO buffer 44 and transmits the data to the RAM buffer 25 via RAM buffer manager 24. Prior to the RAM Port Interface 42 reading data out of the FIFO buffer 44, a read-pointer address register 46 is preset to point to the beginning of data written into the FIFO buffer 44, i.e. the first row in this example. Thereafter, the RAM Port Interface 42 begins reading data segments from the FIFO buffer 44 in synchronism with clock CLK-2. The read-pointer address register 46 is incremented as each data segment is read from the FIFO buffer 44. Once the read-pointer address register 45 is incremented to point to a next buffer row, the present buffer row is free to be written with a next data segment of the data block being transferred.
Since the FIFO buffer 44 holds only 32 4-byte segments (128 bytes or 1024 bits) the buffer 44 typically cannot store an entire disk data block (e.g. 512 bytes or 4096 bits) at once. Accordingly, the FIFO buffer 44 is cycled (rolls over) several times during the transfer of a single block of data. After the data block is both written to and read from the FIFO buffer 44, the write-pointer address register 48 and the read-pointer address register 46 are reset and the above process is repeated for transferring a next data block from the disk drive 30 to the host 22.
In a typical data transfer from the RAM buffer 25 to the disk drive 30, a plurality of data blocks are transferred from the host 22 to the RAM buffer 25 and then the blocks of data are subsequently transferred to the FIFO buffer 44 via the RAM Port Interface 42. Similar to that of transferring data from the drive 30 to the RAM buffer 25, the FIFO buffer 44 presets the write-pointer register 48 to point to the beginning of the FIFO 44. Next, the RAM read/write process control circuit 43 is enabled for writing data to the FIFO buffer 44 while the disk read/write process control circuit 41 is enabled for reading data from the FIFO buffer 44. Thereafter, the RAM Port Interface 42 begins preemptively writing data segments to the FIFO buffer 44 in synchronism with clock CLK-2. This is to ensure that the data is available for transfer to the disk 32 when the head 31 arrives at the correct location over the disk 32. Additionally, the write-pointer address register 48 is incremented as each data segment is written into the FIFO buffer 44. Once the FIFO buffer 44 is filled, the RAM buffer 25 write process pauses and waits for space to become available in the FIFO buffer 44. Space becomes available in the FIFO buffer 44 as a result of the disk interface 45 read process, which reads data from the FIFO buffer 44 and sends the data to the disk channel 37 for subsequent storage on the disk 32. When sufficient space becomes available in the FIFO buffer 44, the process of transferring data from the RAM buffer 25 to the FIFO buffer 44 is resumed. This process is repeated until all data is transferred from the RAM buffer 25 to the disk 32.
Prior to the disk drive interface 45 reading data out of the FIFO 44, the read-pointer address register 46 is preset to the beginning of the FIFO buffer 44. Thereafter, the disk drive interface 45 begins reading data segments from the FIFO buffer 44 synchronously with clock CLK-1. Additionally, the read-pointer address register 46 is incremented synchronously with each data segment read from the FIFO buffer 44. After the data block is both written to and read from the FIFO buffer 44, the write-pointer address register 48 and the read-pointer address 44 are reset and the above process is repeated for transferring the next data block from the host 22 to the disk drive 30.
Generally, the asynchronous operating characteristics of both the RAM 25 and the disk drive 30 with respect to one another cause problems in transferring data therebetween. One such problem occurs as a result of having to reset the write-pointer address register 48 and the read-pointer address register 46 after each data block transfer. Another problem occurs due to the RAM Port interface 42 having to arbitrate to gain access to the RAM buffer 25. Collectively, this arbitration time and the time required to reset the write-pointer register 48 and read-pointer register 46 can cause the FIFO buffer 44 to reject reception of a second data block until the former data block is completely read out of the FIFO buffer 44 and the pointers 46 and 48 have been reset. In transferring data from the disk drive 30 to the RAM 25, this delay may result in forcing the disk drive 30 to wait until the FIFO buffer 44 is again receptive to receiving data. Such buffer access waiting period may cause the disk drive 30 incur another complete revolution of the storage disk 32 to arrive at the same data in a track 33 and then read the data. The wait associated with a second disk revolution to read a track is known in the art as xe2x80x9crotational latencyxe2x80x9d, and excessive rotational latencies degrade disk drive system performance.
Conventional methods of solving this problem have been to simultaneously write to and read from the FIFO buffer 44 without resetting the pointer registers 46 and 48. However, this solution introduces additional problems when a first data block being written to the FIFO buffer 44 is aborted somewhere between the beginning and ending of the data block. When the transfer of the first data block is aborted and the writing of a second data block immediately follows, the read-pointer address associated with the tail end of the aborted first data block can overlap with the write-pointer address associated with the beginning of the second data block being written to the FIFO buffer 44. This data overlap condition causes data from the second data block to be erroneously transferred as data of the first data block.
Another problem occurs when writing a sequence of contiguous data blocks from the disk drive 30 to the FIFO buffer 44, via the disk interface 45, if there is insufficient space in the buffer 44 to accommodate the data. This full condition of the FIFO buffer 44 occurs when the RAM Port Interface 42 cannot read data out of the FIFO 44 fast enough to make room for data being written into the FIFO 44. If the FIFO buffer 44 does not have space for data being written thereto from the disk drive 30, an overflow condition occurs, which can result in a data transfer error.
A similar problem occurs when the RAM Port Interface 42 does not transfer a steady stream of data to the FIFO 44 such that the FIFO 44 runs out of data or underflows. This FIFO underflow condition again results in reduced performance of the disk drive 30, since the disk drive 30 has to incur another rotational latency delay in order to bring the data block track destination beneath the transducer head 31 for data writing during a second pass over the track 33.
Thus, a hitherto unsolved need has remained for a FIFO buffer control method and circuit that facilitates simultaneous multiple block writing to and reading from a FIFO buffer without data overlap. Additionally, a FIFO buffer control circuit and method is needed that does not require a write-pointer register and a read-pointer register to be reset after each data block transfer so that a plurality of contiguous data blocks, which are much larger than the FIFO storage capacity, can be seamlessly transferred back and forth between the disk drive and the host computer.
An object of the present invention is to provide a FIFO buffer control that enables an end of a first data block to occupy a FIFO buffer register simultaneously with a beginning of a second data block without data overlap, in a manner overcoming limitations and drawbacks of the prior art.
Another object of the present invention is to provide a FIFO buffer control that does not require the write-pointer or the read-pointer to be reset after each data block transfer.
In accordance with principles of the present invention, a FIFO buffer control circuit enables a FIFO buffer to simultaneously contain portions of plural adjacent data blocks without data overlap. During a process of transferring data blocks between a sending unit and a receiving unit asynchronously clocked with the sending unit, the FIFO control captures and saves a FIFO buffer write-pointer address that is associated with beginning of a first data block to be written to the FIFO buffer. After writing the first data block to the FIFO buffer, the FIFO control captures and saves a buffer write-pointer address associated with the end of the first data block. Next, the FIFO control captures and saves FIFO buffer write-pointer addresses associated with a beginning of a second data block to be written to the FIFO buffer. After writing the second block to the FIFO buffer, the FIFO buffer control captures and saves a buffer write-pointer address associated with the end of the second data block. This process is repeated for capturing and saving the write-pointer addresses associated with each successive data block written into the FIFO buffer.
Meanwhile, a read pointer address register of the FIFO buffer is loaded with the previously saved write pointer address that corresponds to the beginning of the first data block to be read. Thereafter, data is read from the FIFO buffer until the end of the first data block is detected. At this instant, the read pointer address register is loaded with the saved write-pointer address associated with the beginning of the second data block written to the FIFO buffer. Then, the second data block is read from the FIFO buffer until the end of the second data block is detected. This read process is repeated until all data blocks written into the FIFO buffer by the sending unit have been read out to the receiving unit.
Since the write-pointer address associated with the beginning and ending of each data block written to the FIFO buffer is captured and saved, successive data blocks can be sequentially written thereto without resetting the write-pointer address register. Additionally, since the read-pointer address register is loaded with the write-pointer address associated with the beginning of each data block, the read-pointer address does not have to be reset after each data block is read from the FIFO buffer. Most importantly, the FIFO control circuit enables segments of a plurality of data blocks to occupy the FIFO buffer register simultaneously without data overlap between such blocks, because the beginning and ending pointers of each data block have been previously captured and saved.
These and other objects, advantages, aspects and features of the present invention will be more filly understood and appreciated upon consideration of the following detailed description of a preferred embodiment, presented in conjunction with the accompanying drawings.